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								// Copyright (C) 2018 F4EXB                                                      //
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								// written by Edouard Griffiths                                                  //
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								//                                                                               //
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								// See: http://liquidsdr.org/blog/pll-howto/                                     //
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								// Fixed filter registers saturation                                             //
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								// Added order for PSK locking. This brilliant idea actually comes from this     //
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								// post: https://www.dsprelated.com/showthread/comp.dsp/36356-1.php              //
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								//                                                                               //
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								// This program is free software; you can redistribute it and/or modify          //
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								// it under the terms of the GNU General Public License as published by          //
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								// the Free Software Foundation as version 3 of the License, or                  //
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								//                                                                               //
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								// This program is distributed in the hope that it will be useful,               //
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								// but WITHOUT ANY WARRANTY; without even the implied warranty of                //
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								// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the                  //
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								// GNU General Public License V3 for more details.                               //
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								//                                                                               //
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								// You should have received a copy of the GNU General Public License             //
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								// along with this program. If not, see <http://www.gnu.org/licenses/>.          //
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								///////////////////////////////////////////////////////////////////////////////////
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								#ifndef SDRBASE_DSP_FREQLOCKCOMPLEX_H_
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								#define SDRBASE_DSP_FREQLOCKCOMPLEX_H_
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								#include "dsp/dsptypes.h"
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								#include "export.h"
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								/** General purpose Phase-locked loop using complex analytic signal input. */
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								class SDRBASE_API FreqLockComplex
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								{
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								public:
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								    FreqLockComplex();
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								    ~FreqLockComplex();
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								    void reset();
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								    void setSampleRate(unsigned int sampleRate);
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								    /** Feed PLL with a new signa sample */
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								    void feed(float re, float im);
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								    const std::complex<float>& getComplex() const { return m_y; }
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								    float getReal() const { return m_yRe; }
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								    float getImag() const { return m_yIm; }
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								private:
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								    /** Normalize angle in radians into the [-pi,+pi] region */
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								    static float normalizeAngle(float angle);
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								    float m_a0;
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								    float m_a1;
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								    std::complex<float> m_y;
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								    float m_yRe;
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								    float m_yIm;
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								    float m_freq;
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								    float m_phi;
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								    float m_phiX0;
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								    float m_phiX1;
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								    float m_y1;
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								};
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								#endif /* SDRBASE_DSP_FREQLOCKCOMPLEX_H_ */
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