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PlutoSDR input: completed settings
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@ -32,6 +32,15 @@ void PlutoSDRInputSettings::resetToDefaults()
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m_LOppmTenths = 0;
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m_LOppmTenths = 0;
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m_log2Decim = 0;
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m_log2Decim = 0;
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m_devSampleRate = 1536 * 1000;
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m_devSampleRate = 1536 * 1000;
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m_rateGovernor = RATEGOV_NORMAL;
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m_dcBlock = false;
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m_iqCorrection = false;
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m_lpfBW = 1500000.0f;
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m_lpfFIREnable = false;
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m_lpfFIRBW = 500000.0f;
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m_gain = 40;
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m_antennaPath = RFPATH_A_BAL;
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m_gainMode = GAIN_MANUAL;
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}
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}
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QByteArray PlutoSDRInputSettings::serialize() const
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QByteArray PlutoSDRInputSettings::serialize() const
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@ -41,7 +50,16 @@ QByteArray PlutoSDRInputSettings::serialize() const
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s.writeS32(1, m_LOppmTenths);
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s.writeS32(1, m_LOppmTenths);
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s.writeU32(4, m_log2Decim);
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s.writeU32(4, m_log2Decim);
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s.writeS32(5, m_fcPos);
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s.writeS32(5, m_fcPos);
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s.writeS32(6, m_rateGovernor);
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s.writeBool(7, m_dcBlock);
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s.writeBool(8, m_iqCorrection);
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s.writeFloat(9, m_lpfBW);
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s.writeBool(10, m_lpfFIREnable);
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s.writeFloat(11, m_lpfFIRBW);
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s.writeU64(12, m_devSampleRate);
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s.writeU64(12, m_devSampleRate);
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s.writeU32(13, m_gain);
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s.writeS32(14, (int) m_antennaPath);
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s.writeS32(15, (int) m_gainMode);
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return s.final();
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return s.final();
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}
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}
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@ -63,8 +81,36 @@ bool PlutoSDRInputSettings::deserialize(const QByteArray& data)
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d.readS32(1, &m_LOppmTenths, 0);
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d.readS32(1, &m_LOppmTenths, 0);
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d.readU32(4, &m_log2Decim, 0);
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d.readU32(4, &m_log2Decim, 0);
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d.readS32(5, &intval, 0);
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d.readS32(5, &intval, 0);
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m_fcPos = (fcPos_t) intval;
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if ((intval < 0) || (intval > 2)) {
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m_fcPos = FC_POS_INFRA;
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} else {
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m_fcPos = (fcPos_t) intval;
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}
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d.readS32(6, &intval, 0);
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if ((intval >= 0) && (intval < (int) RATEGOV_END)) {
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m_rateGovernor = (RateGovernor) intval;
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} else {
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m_rateGovernor = RATEGOV_NORMAL;
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}
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d.readBool(7, &m_dcBlock, false);
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d.readBool(8, &m_iqCorrection, false);
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d.readFloat(9, &m_lpfBW, 1500000.0f);
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d.readBool(10, &m_lpfFIREnable, false);
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d.readFloat(11, &m_lpfFIRBW, 500000.0f);
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d.readU64(12, &m_devSampleRate, 1536000U);
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d.readU64(12, &m_devSampleRate, 1536000U);
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d.readU32(13, &m_gain, 40);
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d.readS32(14, &intval, 0);
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if ((intval >= 0) && (intval < (int) RFPATH_END)) {
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m_antennaPath = (RFPath) intval;
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} else {
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m_antennaPath = RFPATH_A_BAL;
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}
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d.readS32(15, &intval, 0);
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if ((intval >= 0) && (intval < (int) GAIN_END)) {
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m_gainMode = (GainMode) intval;
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} else {
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m_gainMode = GAIN_MANUAL;
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}
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return true;
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return true;
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}
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}
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@ -26,11 +26,52 @@ struct PlutoSDRInputSettings {
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FC_POS_CENTER
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FC_POS_CENTER
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} fcPos_t;
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} fcPos_t;
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enum RFPath
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{
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RFPATH_A_BAL = 0,
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RFPATH_B_BAL,
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RFPATH_C_BAL,
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RFPATH_A_NEG,
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RFPATH_A_POS,
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RFPATH_B_NEG,
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RFPATH_B_POS,
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RFPATH_C_NEG,
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RFPATH_C_POS,
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RFPATH_TX1MON,
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RFPATH_TX2MON,
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RFPATH_TX3MON,
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RFPATH_END
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};
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typedef enum {
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GAIN_MANUAL,
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GAIN_AGC_SLOW,
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GAIN_AGC_FAST,
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GAIN_HYBRID,
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GAIN_END
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} GainMode;
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typedef enum {
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RATEGOV_NORMAL,
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RATEGOV_HIGHOSR,
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RATEGOV_END
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} RateGovernor;
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quint64 m_centerFrequency;
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quint64 m_centerFrequency;
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fcPos_t m_fcPos;
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fcPos_t m_fcPos;
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qint32 m_LOppmTenths;
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qint32 m_LOppmTenths;
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quint32 m_log2Decim;
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quint32 m_log2Decim;
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quint64 m_devSampleRate;
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quint64 m_devSampleRate;
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RateGovernor m_rateGovernor;
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bool m_dcBlock;
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bool m_iqCorrection;
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float m_lpfBW; //!< analog lowpass filter bandwidth (Hz)
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bool m_lpfFIREnable; //!< enable digital lowpass FIR filter
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float m_lpfFIRBW; //!< digital lowpass FIR filter bandwidth (Hz)
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uint32_t m_gain; //!< "hardware" gain
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RFPath m_antennaPath;
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GainMode m_gainMode;
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PlutoSDRInputSettings();
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PlutoSDRInputSettings();
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void resetToDefaults();
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void resetToDefaults();
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