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VE7UWU/sdrangel
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mirror of https://github.com/f4exb/sdrangel.git synced 2026-10-08 00:00:42 -04:00
Code Issues Projects Releases Wiki Activity
5,702 Commits 4 Branches 386 Tags
1625ff0450fdbc6be53465e4bd5b5a00467bc0c9
Commit Graph
12 Commits
Author SHA1 Message Date
f4exb 4bb0f4f51a Fixed incomplete copyright headers (2): plugins/samplesource 2019-04-11 06:57:41 +02:00
f4exb 7574cb23d4 Windows: MSVC2017: fixed more attribute unused cases (2) 2018-11-13 08:51:14 +01:00
f4exb 19c32b4354 Removed 24/16 bit differentiation on Decimator instantiation where possible 2018-05-01 23:57:12 +02:00
f4exb d735025c6c With global adoption of even/odd decimators the accu type must be 32 not 64 bits 2018-04-29 10:38:25 +02:00
f4exb 2ddcb8c358 Differentiate Rx and Tx DSP sample sizes 2018-01-22 08:46:05 +01:00
f4exb 732561152b 24 bit DSP fix 2018-01-22 02:49:06 +01:00
f4exb ccb1563299 PlutoSDR input: corrected I/Q loop processing as interleaved and not I/Q sample block 2017-09-10 16:58:48 +02:00
f4exb 6a229bef10 PlutoSDR input: restored soft decimation 2017-09-10 12:27:28 +02:00
f4exb 04d06085fe PlutoSDR: debug (3) 2017-09-10 10:16:23 +02:00
f4exb 3c20b02602 PlutoSDR input: simplify convert method parameters 2017-09-08 08:45:24 +02:00
f4exb 450a44036e PlutoSDR input: fill sample FIFO only when convert buffer is full 2017-09-08 08:41:57 +02:00
f4exb e1c3a66983 PlutoSDR input: added thread class 2017-09-06 06:15:38 +02:00
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