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VE7UWU/sdrangel
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mirror of https://github.com/f4exb/sdrangel.git synced 2026-10-08 00:00:42 -04:00
Code Issues Projects Releases Wiki Activity
4,568 Commits 4 Branches 386 Tags
4032d62b3df74092e9d9dac97a0d916103c1ce73
Commit Graph
11 Commits
Author SHA1 Message Date
f4exb 67f523e629 TestSource: make it more robust 2018-09-06 14:29:14 +02:00
f4exb 19c32b4354 Removed 24/16 bit differentiation on Decimator instantiation where possible 2018-05-01 23:57:12 +02:00
f4exb d735025c6c With global adoption of even/odd decimators the accu type must be 32 not 64 bits 2018-04-29 10:38:25 +02:00
f4exb f01b90094b PVS-Studio static analysis corrections (1) issue #137 2018-02-21 18:54:59 +01:00
f4exb 1d9ab62a4a Test source: added AM and FM modulations 2018-02-11 13:48:17 +01:00
f4exb 373aa6960f Test Source: add phase imbalance control 2018-01-31 22:34:55 +01:00
f4exb 2ddcb8c358 Differentiate Rx and Tx DSP sample sizes 2018-01-22 08:46:05 +01:00
f4exb 732561152b 24 bit DSP fix 2018-01-22 02:49:06 +01:00
f4exb bd8c916dd4 TestSource: implemente DC and IQ bias and corrections 2018-01-14 11:58:36 +01:00
f4exb e3575d5f5f TestSource: fixes 2018-01-14 04:43:24 +01:00
f4exb 34f6b796b7 TestSource: first implementation 2018-01-14 02:25:24 +01:00
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