VE7UWU/sdrangel
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4 Commits

Author SHA1 Message Date
f4exb
660d8d22ae New PLL: heuristics to find locked state 2018-05-16 01:57:16 +02:00
f4exb
bb2d530122 New PLL: phase lock status draft 2018-05-15 19:40:53 +02:00
f4exb
68c50769fe New PLL: implemented trick on the phase comparator for M-ary PSK operation 2018-05-14 19:14:30 +02:00
f4exb
1549ecaa0f New PLL with complex signal input and w, zeta, K parameters 2018-05-13 08:55:14 +02:00