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								 f4exb | 61a16eade9 | Use always 16 bit DSP on Tx side | 2018-01-22 10:46:57 +01:00 |  | 
			
				
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								 f4exb | bacc6659b0 | 24 bit DSP: use a different define for Tx chain so that it can stay on 16 bit DSP | 2018-01-22 03:00:08 +01:00 |  | 
			
				
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								 f4exb | 732561152b | 24 bit DSP fix | 2018-01-22 02:49:06 +01:00 |  | 
			
				
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								 f4exb | ad219d50cc | Implemented 24 bit internal DSP (with bugs ...) | 2018-01-21 21:48:36 +01:00 |  | 
			
				
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								 f4exb | 08ce7f423b | Templatize the accumulator type of integer half-band filters (non SIMD) | 2018-01-21 19:39:51 +01:00 |  | 
			
				
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								 f4exb | 23e5ef76d4 | Device sink engine: fixed adding source channels while it runs | 2018-01-02 11:00:00 +01:00 |  | 
			
				
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								 f4exb | 906d04dd41 | Up/Down channelizers: use input message queue for all message forwarding to sample source/sinks and do not forward unknown messages | 2017-12-29 05:48:54 +01:00 |  | 
			
				
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								 f4exb | c6083ea6f4 | Down/Up channelizers: enqeue MsgChannelizerNotification to sample sink/source instead of processing it directly | 2017-12-29 05:14:40 +01:00 |  | 
			
				
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								 f4exb | f6bc9daf8e | UpChannelizer: pass baseband sample rate in notification message | 2017-08-06 17:10:29 +02:00 |  | 
			
				
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								 f4exb | f74e3b83a7 | Modulators: changed single Tx channel samples feed handling. Pure virtual function is useless | 2016-12-22 23:45:56 +01:00 |  | 
			
				
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								 f4exb | 1afd8df5f9 | Modulators: changed single Tx channel samples feed handling | 2016-12-22 23:39:06 +01:00 |  | 
			
				
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								 f4exb | 7015fb97d2 | Put intrinsics in their own templatized classes | 2016-11-07 04:16:02 +01:00 |  | 
			
				
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								 f4exb | 63d6eea066 | Use more precise SIMD flags and detect actual x86_64 SIMD features | 2016-11-07 00:42:57 +01:00 |  | 
			
				
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								 f4exb | dbbbfa12ee | Changed USE_SIMD flag to USE_SSE | 2016-11-06 02:08:38 +01:00 |  | 
			
				
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								 f4exb | bc3dfb19cd | IntHalfBandFilterEO2: use dual forward and backward buffers to avoid byte shuffling in SIMD instructions. Implemented in the up channelizer | 2016-11-06 01:07:13 +01:00 |  | 
			
				
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								 f4exb | f2a50c0c0f | Use even/odd FIR filter half band interpolator only if SIMD is available | 2016-11-04 22:47:09 +01:00 |  | 
			
				
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								 f4exb | 9f74c82715 | IntHalfBand FIR filter SSE optimizations | 2016-11-04 01:12:39 +01:00 |  | 
			
				
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								 f4exb | 5d5593bda7 | Tx ph.2: put the double buffered FIR interpolator and decimator in its own class | 2016-11-01 15:02:50 +01:00 |  | 
			
				
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								 f4exb | bd4d224166 | Tx ph.2: IntHalfBandFilter: use double buffer technique for interpolation. Use it with the UpChannelizer and increase order to 96 for better spur rejection. Moreover it is still more CPU efficient | 2016-11-01 05:54:25 +01:00 |  | 
			
				
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								 f4exb | f5bbbb7cab | Tx ph.2: UpChannelizer: allow any sample rate | 2016-10-30 22:01:20 +01:00 |  | 
			
				
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								 f4exb | 91315913b4 | Tx ph.2: change UpChannelizer filter chain from std::list to std::vector | 2016-10-30 18:22:33 +01:00 |  | 
			
				
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								 f4exb | 4a001350d3 | Tx ph.2: Templatized IntHalfbandFilter and improved coefficients. Changed to order 80 for upsamplers and 48 for downsamplers | 2016-10-29 17:01:02 +02:00 |  | 
			
				
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								 f4exb | 4ab45f4768 | Tx ph.2: Fixed half-band interpolators and set the order to 64 (for all) | 2016-10-29 12:29:24 +02:00 |  | 
			
				
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								 f4exb | e9f0bb0d45 | Tx ph.2: UpChannelizer: interpolator (1) draft | 2016-10-28 18:39:45 +02:00 |  | 
			
				
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								 f4exb | 119127fdab | Tx ph.1: Fixes to file sink GUI and some debug messages | 2016-10-23 02:22:00 +02:00 |  | 
			
				
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								 f4exb | b56c2d9a2c | Tx ph.1: new classes (1) | 2016-10-17 08:58:49 +02:00 |  |