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VE7UWU/sdrangel
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mirror of https://github.com/f4exb/sdrangel.git synced 2026-08-26 13:26:24 -04:00
Code Issues Projects Releases Wiki Activity
3,092 Commits 3 Branches 386 Tags
bdf5a4ef080d4a5dfc1b93795b8d40a7147d68a5
Commit Graph
11 Commits
Author SHA1 Message Date
f4exb 5598265e66 Multiple modulators support: works with two modulators 2016-12-26 12:11:51 +01:00
f4exb e05822ba02 Implement own FIFO in BasebandSampleSource. SampleSourceFIFO: remove useless chunk size completely and set initial fill to only half the FIFO size 2016-12-23 14:29:42 +01:00
f4exb 1afd8df5f9 Modulators: changed single Tx channel samples feed handling 2016-12-22 23:39:06 +01:00
f4exb 441c2c1817 Send number of samples to write in the writeData signal. Ask for half the buffer size when more than half of it is consumed 2016-12-21 02:24:49 +01:00
f4exb 0fc6d95357 Tx ph.1: fixed read pointer management when getting new samples 2016-10-25 03:31:36 +02:00
f4exb ee55747c0b Tx ph.1: FileSink: set sample source FIFO size depending on sample rate 2016-10-25 02:34:29 +02:00
f4exb 289c1a203f Tx ph.1: Sample source FIFO read with signal. Use a specific spectrum sink (vis) reference in Device sink engine for main spectrum rendering 2016-10-24 18:06:44 +02:00
f4exb 8f70840561 Tx ph.1: fixed sample source FIFO 2016-10-23 23:27:19 +02:00
f4exb 4e446b9c7a Tx ph.1: fixed source sink initialization 2016-10-23 14:14:32 +02:00
f4exb 52b618469c Tx ph.1: refactored source sample FIFO. StarUML model: added Tx classes 2016-10-15 09:53:06 +02:00
f4exb 6e82cb37b8 Tx support: added a sample source FIFO class 2016-10-10 01:13:12 +02:00
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