6 Commits

Author	SHA1	Message	Date
f4exb	058f3d5af8	RTLSDR: optimized decimator	2018-05-02 00:24:50 +02:00
f4exb	2ddcb8c358	Differentiate Rx and Tx DSP sample sizes	2018-01-22 08:46:05 +01:00
f4exb	732561152b	24 bit DSP fix	2018-01-22 02:49:06 +01:00
f4exb	ad219d50cc	Implemented 24 bit internal DSP (with bugs ...)	2018-01-21 21:48:36 +01:00
f4exb	08ce7f423b	Templatize the accumulator type of integer half-band filters (non SIMD)	2018-01-21 19:39:51 +01:00
f4exb	c7e1526930	Added decimation class with unsigned to signed conversion with shift. Applied to RTL-SDR	2018-01-16 00:01:38 +01:00